Verification Engineer Job in Multiple locations at Smartsoc Solutions
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Verification Engineer

Smartsoc Solutions

Chennai, Bangalore, Hyderabad

Start date
Starts Immediately
CTC
12 LPA
Apply By
22 Dec' 22
Posted 3 weeks ago
Fresher Job
About Smartsoc Solutions
SmartSoC Solutions is emerging as a leader in providing engineering solutions worldwide. We offer end-to-end semiconductor, embedded, and IT services to design and build next-generation leadership products under one roof while allowing clients to achieve both quick wins and long-term results. Our goal is to be an extended arm of engineering products and IT companies and ensure good quality productization cost-effectively.

SmartSoc Solutions offers the following end-to-end and partial solutions: SOC design & verification, physical design & verification, DFT, FPGA design & emulation, analog design & layout

SmartSoC Solutions has grown from strength to strength. We currently have over 500 employees with offices in multiple cities in India, the USA, Singapore, Sweden, Finland, the USA, the UK, South Korea, and more upcoming.
Activity on Internshala
Hiring since November 2022
1 opportunity posted
About the job
Key responsibilities:

1. Work on being exposed to the latest verification methodologies like UVM and enable complex feature verification suites
2. Architect and develop block-level verification environments for sub-system and full-chip using System Verilog and UVM methodology
3. Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems
4. Use various front-end simulator tools (VCS/NC) to perform this activity
5. Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage, and gate-level simulation
6. Develop Perl, Python, and/or shell scripts to improve current verification infrastructure/methodology

Skills & Requirements:

1. ASIC verification using SystemVerilog
2. Experience in constrained-random verification is a strong plus
3. Experience with verification methodology like OVM/VMM/UVM
4. Perl/Tcl scripting is strongly preferred
5. Strong problem-solving and ASIC debugging skills
Skill(s) required
SystemVerilog UVM Verilog
Salary

Annual CTC: 12 LPA (All fixed)

Perks
5 days a week Health Insurance
Number of openings
20

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